A variety of techniques have been developed to increase the overall processing speed of computer systems. Vast improvements in integrated circuit processing technologies have contributed to the ability to increase computer processing speeds and memory capacity, thereby contributing to the overall improved performance of computer systems. The ability to produce integrated circuits with sub-micron features enables the amount of electrical components, such as capacitors, per integrated circuit to also increase.
Dynamic random access memory (DRAM) chips, comprised of large arrays of capacitors with sub-micron features, are utilized for main memory in computer systems. DRAM is typically inexpensive and high density, thereby enabling large amounts of DRAM to be integrated per device. Due to the inherit nature of capacitors, DRAM must continuously be refreshed or the data stored within the capacitor will be lost. Each capacitor slowly leaks charge, and if the DRAM is not refreshed, eventually the capacitors will leak enough charge and encounter irreversible data corruption.
Most DRAM chips sold today are compatible with various double data rate (DDR) DRAM standards promulgated by the Joint Electron Devices Engineering Council (JEDEC). The standards provided by JEDEC provide a refresh cycle time that prevents the access of data for a period of time. Increasing DDR DRAM device density within a computer system increases the amount of time required for refresh, and thereby increases computer processing latency.
In order to address these issues, JEDEC adopted a feature in the DDR version four (DDR4) standard known as 1×, 2×, and 4× refresh mode. In these modes, a DDR4 memory can refresh a selected bank, one half of the selected bank, or one fourth of the selected bank, respectively, in response to a single refresh (REF) command. A mode register, mode register 3 (MR3), is used to select between these modes. Moreover, MR3 can also be programmed to support “on-the-fly” modes in which the choice of 1× or 2×, or the choice of 1× or 4×, can be performed dynamically and indicated by an unused address bit.
In the following description, the use of the same reference numerals in different drawings indicates similar or identical items. Unless otherwise noted, the word “coupled” and its associated verb forms include both direct connection and indirect electrical connection by means known in the art, and unless otherwise noted any description of direct connection implies alternate embodiments using suitable forms of indirect electrical connection as well.